1. Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing floating gates, and more particularly, to a method of improving erase characteristics and coupling ratios of semiconductor memory devices employing floating gates.
2. Description of the Prior Art
One class of semiconductor memory devices employ floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represent binary information. These are called electrically programmable readonly memories (EPROM). EEPROMS are erasable electrically programmable read only memories. "Flash" memory devices are those in which all of the cells can be erased in a single operation. A buried bit line Flash EPROM/EEPROM has the advantage of smaller cell size when compared with conventional Flash cells because the buried bit line structure is contactless. However, a major problem with the buried bit line Flash cell is the unexpected performance of flash erase characteristics. This is believed to result from the non-uniform thin tunnel oxide thickness near the source edge, as noted in U.S. Pat. No. 4,780,424 to Holler et al.
Several methods have been proposed to improve the erase characteristics of the buried bit line process. U.S. Pat. Nos. 5,106,772 to Lai, 5,077,230 and 5,075,245 both to Woo et al., and 5,012,814 to Woo describe methods of using thin nitride, short reoxidation, or using no sacrificial oxide. These are still rough processes which may produce devices which are inconsistent in erase characteristics from lot to lot. U.S. Pat. No. 5,106,772 uses polysilicon deposition immediately after tunnel oxide growth to maintain the quality of the oxide, but it cannot avoid the birds-beak encroachment of thicker oxide into the thin tunnel oxide area near the source/drain edge so that the source/drain junctions will be under the non-uniform birds-beak region.